1. Field of Invention
The present invention relates to a fabrication method for a semiconductor substrate. More particularly, the present invention relates to a fabrication method for a gate spacer.
2. Description of Related Art
Concurrent with an increase in semiconductor device integration, it is common to decrease the size of the circuit structure device according to design rules, which gradually minimizes an integrated circuit (IC) device. However, the circuit resistance increases as the size of the semiconductor circuit design decreases without any material change.
Conventionally, several methods have been developed to solve the problem of increased sheet resistance from the interface between a polysilicon gate and a source/drain (S/D) region. One of these methods is a self-aligned silicide (salicide) process, which forms a silicide on the surface of the polysilicon gate and the S/D region to reduce the sheet resistance of the polysilicon gate and the S/D region.
However, since the surface area of the polysilicon gate and the S/D region for forming the silicide has become very small in the deep sub-micron process, a narrow linewidth effect readily occurs in the salicide process. One conventional method of increasing the area for forming the silicide is to over-etch the gate spacer, so that the height of the spacer is reduced. As a result, the top edge of the polysilicon gate is exposed to increase the surface area for forming the silicide.
Although this solves the problem related to the sheet resistance of the polysilicon gate, other problems develop. As the over-etching time lengthens, the height of the spacer decreases and the width of the spacer also reduces. Despite the increased surface area of the gate for forming the silicide, the width reduction of the spacer causes other related problems; for example, the width reduction of the lightly doped drain (LDD) leads to an enhanced short channel effect. Thus, it is not easy to control the duration of the over-etching process, which reduces the height of the spacer. In addition, the substrate surface of the S/D region is exposed during the over-etching process, so that the surface is damaged as a result of an increased etching time, leading to the problem of leakage current.